Biasing of Dual Gate Fets
The problem with using FETs of all kinds is the wide part-to-part
variation. Look at the specs for the BF998 - many of the critical specs
show only a maximum or minimum, but not both, or just a typical value.
You can be way off if you simply use a "typical" set of curves. If you
want to do an analytical design with a part with non-specifications like
this is to use a curve tracer to generate curves for the individual
part, then use those curves for your design. Pull another part of the
same part number from your drawer, and you'll need a different design.
This exercise is useful for educational purposes, but it isn't a
technique you can use to design something that can be easily duplicated.
That's probably why you don't see a lot of FETs being used in commercial
products, except in applications where there's a lot of feedback to
stabilize the operating point, such as source followers, or when simply
nothing else will do. Even then, the manufacturer has probably paid the
vendor to select parts with a much narrower, and well specified, range
of characteristic values. That's been my experience in designing
commercial electronic test equipment.
Roy Lewallen, W7EL
David wrote:
Tim,
Say we look at VG1s = 0.1V as per your example.
The graph for BF998 shows that if VG2s = 4V and VDs = 8V then ID approx
= 12.5mA
This would mean that unless I applied a negative voltage on the source I
would need to apply 0.1V forward bias to G1 and 4V to G2 ?
As Rs is creating a negative self bias voltage ?
If I set the bias point lower - say 5mA then VG1s is approx. -0.2V
according to the graph.
I can achieve this by using a resistor in the source of 0.2/5mA (40
Ohms) and then set VG1 = 0 (so that VG1s = -0.2V) and then 4.2V on G2
so that VG2s = 4V.
Is this correct ?
The transfer characteristic curve shows that for say 10mA. If VG2s = 4V
then gm = around 24mS and if VG2s is reduced to 0V the gm reduces to
about 7mS.
Thanks
regards
David
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