RadioBanter - View Single Post - “IBiquity announces 1.5 million HD chipsets shipped.” Wow! More B.S.

Telamon · October 15th 08, 03:09 AM posted to rec.radio.shortwave

In article
,
wrote:

On Oct 10, 9:27*pm, Telamon
wrote:
In article
,

wrote:
On Oct 9, 2:45*pm, Telamon
wrote:
In article
,

wrote:
On Oct 9, 11:42*am, Telamon
wrote:
In article
,

wrote:
On Oct 8, 7:12*pm, Telamon

wrote:
In article

m,

*Rfburns wrote:
³IBiquity announces 1.5 million HD chipsets shipped.² *Wow!
More
B.S.

Struble, I know you read this column because I¹ve been
asking you to produce benchmarks for your bogus company
for months.

Lets see now, with million and millions spent so far that
makes somewhere around $250,000 per radio/chipset. Give
or take $100,000 or so and I¹m sure your figure of 1.5
million is suspect. Like every other statistic you
produce from your fertile but screed-up imagination.

Interesting that iBiquity announces the number of
chipsests shipped, not to confuse that with the
insignificant number of receivers sold.

Hybrid digital is failing Struble but keep reading this
message board.

Struble, it must be very tiring for you to constantly
find new ways to distort the facts about your defective
hybrid digital scam.

Money¹s a little tight now also. *Hope it dries up for
you real soon.

That's BS. There has not been enough time to produce 1.5
million chipsets even if production started when it was
supposed too.

Six years should be plenty of time for 1.5 million chipsets.

It has only been a few months since the HD chips were supposed
to be made. What has been used until now are general purpose
DSP chips programmed to perform the HD decoding. As such they
very inefficient and everyone has been waiting for parts
specifically designed to perform this function.

So as I said there has not been enough time.

You can't make such a definitive statement since you don't know
who fabbed the chips.

None has yet as far as I can tell.

Say the test time was long, say 1 second. Allocate a modest
number of handlers, say 10. So it's effectively pumping out 10
chips a second. That's 42 hours of elapsed time. Even with one
tester, it wouldn't be much of an issue.

You are dreaming if you think these chips can be tested in 1
second. It would be more like 20 to 30 seconds. In addition part of
the testing process might be writing or burning the programming
instructions. Writing is always a slow process.

Even if the chip is fabricated with the software fully imbedded so
no firmware writing takes place you have to test all the codex in
the chip that's not very fast. This will take time. It always boils
down to how thoroughly you want to test the chip. Just a few
vectors here is not going to do the job.

And you know what, you skipped over the whole test program writing
process, which together with the hardware minimum of a socket
design and a DIB will take a few months.

Also, we don't know how many chips are in the chip set, but I
don't see test time as a show stopper.

It is supposed to be two chips. One chip handles the RF/analog part
and the other the DSP and codec processing. Those two parts are
supposed to have minimal support parts to function. There would
also be the components for the audio output stage to drive
speakers.

How long would it take to make that many chips? You haven't
stated the die size. Figure on 0.2x0.2 inch and 50 square inches
on an 8 inch wafer, or 1250 per wafer. Figure 1000 die make it
past final test. That means 1500 wafers. A fab like TSMC could do
around 50K wafers per month, so making 1.5 millions units isn't a
big deal.

You think the first production run is going to be 1.5 mil units?
TSMC is a busy place. You would have to wait months to get that
kind of capacity going your way. Besides there are production steps
that have to be completed before anything can actually be
fabricated. You know this, tape out, and then mask generation, then
at least one small production run so the design/fabrication process
is verified before going to full production.

I hate IBOC, but it is totally possible they shipped that many
chipsets.

I don't think so. Sounds more like marketing hype to me. I can't
find any data on a HD - IBOC chip set other than announcements to
do so. No data sheets, no application notes, no reference designs =
vaporware.

I recall years ago when those stupid Japanese toys that you had
to "keep alive" where shipping, much of the world wafer capacity
was dedicated to making the chips.

I speculate that the programming that operates in the chip has not
been well defined and has been changing over time. This presents a
problem for a chip that is completely hardwired because if the
standard changes then the parts are junk and have to be trashed.
Then you spin changes in one or more masks and fabricate again.
Very expensive.

While I've mostly designed mixed mode chips, I have done digital too.
The buzzword (ok, phrase) is design for test, if not built in test.
No way would a well designed chip sit on the tester for 20 seconds.

You are dreaming. You could test an amplifier or simple logic in a
second or two but not large ASIC's.

So you would make the chip even more expensive with built in pattern
generation, detection, and error logic? You realize that it does not
matter where the pattern generation and matching takes place it still
takes the same amount of time.

There are two expensive pieces of machinery in chip testing: the ATE
and the handler. A jellybean chip occupying an expensive handler is
no way to make money. Generally they go for an more expensive ATE to
test the part faster. [Handlers are really a mechanical pain in the
ass.]

You don't have much choice with ASIC's running a lot of code. Patterns
running at speed take several seconds each. If you have to repeat that
for several scenarios that the chip has to handle, well, that adds up.

I've done worse. Sure the DC stuff takes a second or two but I've had
parts take almost a minute to run all the test vectors at speed. If you
want a full test that's what you have to do.

Yeah it's expensive to tie up multi-million dollar testers but you risk
shipping bad product not having at least 85 to 90% coverage.

If not TSMC, then other fabs. Nobody is really at full capacity in the
Bush economy. Chips I've done for consumer electronics companies
(Sony, Mitsubishi, etc.) generally do a few hundred K right away, just
to stock the stores. Now if the HD chips are shared across a few
companies, I could see a million being made. It's really not that big
of a deal.

Now can they sell a million crappy radios? Who knows. Not to me.

Not everyone is up to date with the latest processes as it is very
expensive. You have to go to a handful of fab's to get the latest
technology for power savings.

The DSP chip is not a cheap part to make and have long test times. The
RF base band chip could be tested in 5 to 10 seconds. What would take
the longest here is the LO and PLL testing with lock times in the tens
of milliseconds. Test time would depend on how many different
frequencies you wanted to check or check locking ranges. Measuring
aspects like phase noise takes time.

Well, whatever. I know what chips I've designed and stand by my
statements. You don't test a chip in its intended function, You test
it as logic. Chips run at megahertz speed. You can do a hell of a lot
of testing in a second.

Now analog chips can take longer to test than digital chips. There are
settling time issues, both in the chip and ATE.

Test time is part of the product cost. You don't get the product past
planning if you can't test it quickly. Well, at least no chip company
I ever worked at ignored test time.

Well, for starters you seem to be forgetting about the humongous
processing times though the DSP chip that amounts to seconds.

You can't test the chip to it's performance specifications if you don't
have it process a large amount of data. You seem to have experience with
fairly simple logic. You can skip the performance testing and just run
functional vectors to check gates in a few seconds as a logic test but
the customer failure rate will go up.

I have not designed chips. I have designed test software and hardware
and yes test time reduction is a test engineering function. Everybody
understands that test time costs the company money.

--
Telamon
Ventura, California