On Thu, 12 Aug 2004 08:28:41 -0700, John Larkin wrote:

On Thu, 12 Aug 2004 02:58:57 GMT, Fred Bloggs
wrote:



John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

LOL. That was an astute observation, not that I'm surprised. Either
I didn't read that part of the book ( I have a NOV '82 Siliconix
data book that sufficed) or I blew it off.

Good point. Bowick seems to be applying the jfet gate-voltage equation
backwards to enhance it! The other example on page 120 is even
sillier.

I *do* remember reading *that*. 0 + 2.48 = 0 for sufficiently small
values of 2.48, yup. I better compare all his refs to my own
collection of app notes in der future and check the math.

Just shows you that an RF expert can't always handle DC.


It's his math, actually. See my other post and while you're at it,
reply to my reply to the idiot so he can see it. A blank post will
suffice -)

--
Best Regards,
Mike