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IF Freq for SDR sampling
I'm trying to get an idea of some of the tradeoffs involved in
determining where to perform the analog to digital conversion for a SDR design which uses 200 MHz as the first IF (pick due to SAW filter availability and it's high enough to simplify the front end filter bank ... the receiver is a homebrew type intended to cover .5 - 600 MHz with a maximum signal bandwidth of 200 kHz). Some options: 1) Sample at the first IF using subsampling. Advantages: Eliminates the need for an additional LO and mixer. Disadvatages: Brad Evans points out in a comp.dsp article entitled "Undersampling (was: RF/IF digital receiver)" that using a high IF means that it will be more sensitive jitter in the ADC clock. The LTC2203 does 25 Msps with a 16 bit output and has a front end which can handle 380 MHz. The AD7763 does 40 Msps with a 24 bit output and includes a digital FIR. However, it's not clear to me what's the maximum frequency that it can handle. What's very interesting is that Analog Devices has an evaluation kit (EVAL-AD7763) available from Digikey for only 163 dollars and it includes (according to the literature) a BF537 EZ-KIT Lite. This appears to be a very inexpensive way to experiment with SDR. 2) Convert the first IF to a second IF of 21.4 MHz and then subsample. Advantages: Less sensitive to ADC clock jitter. Many different crystal filter are available for 21.4 MHz from places such as Network Sciences. This allows additional filtering to be done in the analog domain which should increase sensitivity. Disadvantages: Involves an additional LO and mixer which means more noise. ADSimPLL says the LO noise is -114 at 10 kHz. Mixer spurs at 7x8 and 8x9. I'm assuming that the spurs are not that interesting given I'm using a LT5512 which is a double balance mixer (i.e. even harmonics don't occur). I imagine that the AD7763 will handle subsampling 21.4 MHz. 3) Convert the second IF to a third IF of 2.9 MHz and sample using a AD9874. Advantages: The AD9874 also contains AGC and an I/Q demodulator in addition to a LO PLL and mixer. This means that the DSP doesn't have to handle these chores. Disadvantages: Involves an additional LO and mixer which means more noise. ADSimPLL says the LO noise is -119 at 10 kHz. Mixer spurs at 6x7, 7x8, and 8x9. I'm assuming that the spurs are not that interesting given the AD9874 mixer is a double balance type (i.e. even harmonics don't occur). BTW: I'm willing to sacrifice some performance if it means making the hardware easier to build (i.e. allows for more slop in the PC layout and assembly). What are peoples thoughts, opinions, and experiences regarding these types of tradeoffs? -- John |
IF Freq for SDR sampling
On Jul 1, 12:12 am, Eric Jacobsen wrote:
Sounds to me like the IF plan is a little screwy already, since the 200MHz IF is in the tuning band of 0.5 to 600MHz. Not sure how well that's gonna work for ya. Okay ... I need to pay attention to spurs from the first IF mixer when working out a frequency plan. For the sake of the original question let's assume that the RF range has been changed to one which is appropriate for a 200 MHz IF. The question still being regarding the tradeoffs of where to digitize the signal. Followup question being ... any good guidelines for picking the first IF frequency other than: 1) High enough to simplify the input filters. 2) Something that is easy to build / buy a good filter for use after the mixer. 3) Something that results in a minimum amount of spurs from the mixer. 4) Something that isn't so high as to complicate construction more than necessary. -- John |
IF Freq for SDR sampling
Hi John,
The BF537 EZ-KIT Lite + AD7763 for less than US$180 looks like a brilliant deal to me, but won't you need I as well as Q channel ADCs ? I am not sure how much enthusiasm I can muster for a BF537 when only packaging available is 192 or 208 BGA, it sounds like a project that is always destined to be a prototype board. It does look like a very capable DSP however. If you want to experiment with SDR, does it get any simpler than SoftRock 40 ? I guess I have a natural inclination to use a platform where there is an established user base - hence plenty of help and support. My other inclination is also to try and keep the sample rate as low as possible, so there are plenty of un-optimized-code CPU cycles available to allow swift algorithm development rather than scrambling around for every last CPU cycle at the start of a project. Having said that all out loud, my inclination is to go for a decent DDS LO, for front end agility, sampling down to a high sample rate (192kHz) stereo (I + Q) audio ADC and to take it from there in DSP. With that all under my belt, then time to look at higher performance solutions, once the question is better understood. Regards, Mark On Jul 1, 11:57 am, wrote: I'm trying to get an idea of some of the tradeoffs involved in determining where to perform the analog to digital conversion for a SDR design which uses 200 MHz as the first IF (pick due to SAW filter availability and it's high enough to simplify the front end filter bank ... the receiver is a homebrew type intended to cover .5 - 600 MHz with a maximum signal bandwidth of 200 kHz). Some options: 1) Sample at the first IF using subsampling. Advantages: Eliminates the need for an additional LO and mixer. Disadvatages: Brad Evans points out in a comp.dsp article entitled "Undersampling (was: RF/IF digital receiver)" that using a high IF means that it will be more sensitive jitter in the ADC clock. The LTC2203 does 25 Msps with a 16 bit output and has a front end which can handle 380 MHz. The AD7763 does 40 Msps with a 24 bit output and includes a digital FIR. However, it's not clear to me what's the maximum frequency that it can handle. What's very interesting is that Analog Devices has an evaluation kit (EVAL-AD7763) available from Digikey for only 163 dollars and it includes (according to the literature) a BF537 EZ-KIT Lite. This appears to be a very inexpensive way to experiment with SDR. 2) Convert the first IF to a second IF of 21.4 MHz and then subsample. Advantages: Less sensitive to ADC clock jitter. Many different crystal filter are available for 21.4 MHz from places such as Network Sciences. This allows additional filtering to be done in the analog domain which should increase sensitivity. Disadvantages: Involves an additional LO and mixer which means more noise. ADSimPLL says the LO noise is -114 at 10 kHz. Mixer spurs at 7x8 and 8x9. I'm assuming that the spurs are not that interesting given I'm using a LT5512 which is a double balance mixer (i.e. even harmonics don't occur). I imagine that the AD7763 will handle subsampling 21.4 MHz. 3) Convert the second IF to a third IF of 2.9 MHz and sample using a AD9874. Advantages: The AD9874 also contains AGC and an I/Q demodulator in addition to a LO PLL and mixer. This means that the DSP doesn't have to handle these chores. Disadvantages: Involves an additional LO and mixer which means more noise. ADSimPLL says the LO noise is -119 at 10 kHz. Mixer spurs at 6x7, 7x8, and 8x9. I'm assuming that the spurs are not that interesting given the AD9874 mixer is a double balance type (i.e. even harmonics don't occur). BTW: I'm willing to sacrifice some performance if it means making the hardware easier to build (i.e. allows for more slop in the PC layout and assembly). What are peoples thoughts, opinions, and experiences regarding these types of tradeoffs? -- John |
IF Freq for SDR sampling
On Sat, 30 Jun 2007 16:57:19 -0700, john wrote:
I'm trying to get an idea of some of the tradeoffs involved in determining where to perform the analog to digital conversion for a SDR design which uses 200 MHz as the first IF (pick due to SAW filter availability and it's high enough to simplify the front end filter bank ... the receiver is a homebrew type intended to cover .5 - 600 MHz with a maximum signal bandwidth of 200 kHz). Some options: 1) Sample at the first IF using subsampling. Advantages: Eliminates the need for an additional LO and mixer. Disadvatages: Brad Evans points out in a comp.dsp article entitled "Undersampling (was: RF/IF digital receiver)" that using a high IF means that it will be more sensitive jitter in the ADC clock. The LTC2203 does 25 Msps with a 16 bit output and has a front end which can handle 380 MHz. The AD7763 does 40 Msps with a 24 bit output and includes a digital FIR. However, it's not clear to me what's the maximum frequency that it can handle. What's very interesting is that Analog Devices has an evaluation kit (EVAL-AD7763) available from Digikey for only 163 dollars and it includes (according to the literature) a BF537 EZ-KIT Lite. This appears to be a very inexpensive way to experiment with SDR. 2) Convert the first IF to a second IF of 21.4 MHz and then subsample. -- snip -- 3) Convert the second IF to a third IF of 2.9 MHz and sample using a AD9874. -- snip -- I think you may be overdoing your concern on the sampling clock. The jitter that matters is the amount of time jitter on the clock. If you can generate a tone that's pure enough to down-convert the 1st IF, then you can generate a clock that's pure enough to down-sample. In either case, if you're crystal controlled you'll probably be much more stable than the LO with which you're doing your first conversion. At this point you need to ask not can you _generate_ a time base that's low enough jitter to do good sampling, but can you _preserve_ the clean signal through your entire sampling path, starting with whatever logic generates the clock, all the way through to the actual sampling. If the sampling takes place inside the ADC then you need to hope (or verify from the data sheet) that the ADC isn't introducing much jitter. If you're really concerned about this then you could make your own sampler with appropriate components to insure the jitter is within your control. -- Tim Wescott Control systems and communications consulting http://www.wescottdesign.com Need to learn how to apply control theory in your embedded system? "Applied Control Theory for Embedded Systems" by Tim Wescott Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html |
IF Freq for SDR sampling
wrote: I'm trying to get an idea of some of the tradeoffs involved in determining where to perform the analog to digital conversion for a SDR design which uses 200 MHz as the first IF (pick due to SAW filter availability and it's high enough to simplify the front end filter bank ... the receiver is a homebrew type intended to cover .5 - 600 MHz with a maximum signal bandwidth of 200 kHz). Each frequency conversion inevitably reduces the IP3 and the KP of the receiver. The other problem with the multiple conversions is the feedthrough of the harmonics and intermods of the heterodynes to the input of the receiver; this creates the "deaf" points in the frequency range. So, the intention is avoiding multiple conversions unless it is really necessary. The multiple conversion could be necessary if the high attenuation of the adjacent channel is required and if the desired channel bandwidth is too narrow. It is difficult to make a good narrowband filter for the high IF. Some options: 1) Sample at the first IF using subsampling. Advantages: Eliminates the need for an additional LO and mixer. Disadvatages: Brad Evans points out in a comp.dsp article entitled "Undersampling (was: RF/IF digital receiver)" that using a high IF means that it will be more sensitive jitter in the ADC clock. The clock jitter can be taken care off. The suppression of the aliases is determined by the 1st IF filter. You will need a good filter, especially if subsampling. [...] What are peoples thoughts, opinions, and experiences regarding these types of tradeoffs? It depends. What are the final parameters of the receiver that you are planning to achieve? What benefits do you expect from doing the processing in the software? How much of time and money do you have? Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com |
IF Freq for SDR sampling
On Jul 1, 6:44 am, MarkAren wrote:
The BF537 EZ-KIT Lite + AD7763 for less than US$180 looks like a brilliant deal to me, but won't you need I as well as Q channel ADCs ? The intent would be to implement a digital downconverter in the DSP. That of course begs the question of how much horsepower is necessary to implement a DDC? I know people are doing it using FPGA, however I haven't seen anyone doing it using a DSP. Another option would be to insert a AD6620 which is a digital down converter. -- John |
IF Freq for SDR sampling
On Jul 1, 1:27 pm, Vladimir Vassilevsky
wrote: What are the final parameters of the receiver that you are planning to achieve? Defined as the best as I can implement without having a mental breakdown, going broke, getting into trouble with the wife, or taking forever. I realize that in the real world the requirements should be a little more concrete. What benefits do you expect from doing the processing in the software? Flexibility and learning. How much of time and money do you have? A lot of time ... one advantage of this being a hobby project is no deadline. Money is flexible, not unlimited (I do have to answer to the wife), say $ 1000 US dollars (more if spread over a longer period of time :-). -- John . |
IF Freq for SDR sampling
On Jul 1, 8:19 am, wrote:
Noise figure and spurious responses are really determined by RX input filters and the first stages of RF amplification. generally at VHF and above you do not get an acceptable NF without an RF amp for communications uses. I was considering a Hittite HMC580ST89 InGaP HBT Gain Block which has a NF of 2.8, covers DC - 1 GHz, and is easy to use (i.e. can operate directly from +5V). The mixer will produce spurs from several causes.. Dirty LO source, for that range I assume you using a carefully designed PLL as DDS has many discrete spurs. Currently the design calls for using a AD9952 DDS followed by a 10.7 MHz BW=300 kHz crystal filter to provide the reference for a ADF4002 PLL controlling a UMC VCO. ADIsimPLL claims phase noise of -107 at 10 kHz. -- John |
IF Freq for SDR sampling
On Sun, 01 Jul 2007 11:18:12 -0700, wrote:
On Jul 1, 6:44 am, MarkAren wrote: The BF537 EZ-KIT Lite + AD7763 for less than US$180 looks like a brilliant deal to me, but won't you need I as well as Q channel ADCs ? The intent would be to implement a digital downconverter in the DSP. That of course begs the question of how much horsepower is necessary to implement a DDC? I know people are doing it using FPGA, however I haven't seen anyone doing it using a DSP. Another option would be to insert a AD6620 which is a digital down converter. -- John If the sample rate is low enough there's no reason the DDC can't be done in software. Since your signal is narrow that might be possible if you can sort out the IF issues and the IF filter bw. Eric Jacobsen Minister of Algorithms Abineau Communications http://www.ericjacobsen.org |
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