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"W3JDR" wrote in message ... Anyone know of a PIC-based frequency locked loop for VFO control? I'm looking for something that can be programmed with a frequency word, and then it aquires and maintains the frequency. I've seen frequency 'stabilizers' but most of them just hold the frequency once it's been manually set. There are also PIC-assisted DDS designs, but these are more complex thatn I want, use more power then I'd like, and are not as clean as a simple voltage controlled oscillator. A number of the MicroChip MPs have 16-bit internal counters that claim to run as high as 50 MHz. The carry out of that counter could be used to cause an interrupt to extend the number of bits in the count. But you would need to precede the count chain with a gate of known and accurate count-window duration. I've thought about the subject and would try a 74AC-series flip-flop as the "gate". The gating control signal would be applied to its DC-reset. A 74HC4060 running with a "32" kHz clock crystal could provide the gating signal. Properly biasing the flip-flop's clock input might result in fairly good sensitivity. These MicroChip MPs have a pulse-width-modulated [PWM] output, but it's only 8- or 10-bit resolution. It could be dithered for more resolution, but that would require an even greater time-constant in the AFC applied to the VCO - probably intolerable. A simple, inaccurate, 8-bit D-to-A chip might be used for rough AFC voltage, with interpolation using the PWM. WARNING: All the above is just hand-waving. 73 de bob w3otc |
PIC Frequency Locked Loop
"W3JDR" wrote in message ... Anyone know of a PIC-based frequency locked loop for VFO control? I'm looking for something that can be programmed with a frequency word, and then it aquires and maintains the frequency. I've seen frequency 'stabilizers' but most of them just hold the frequency once it's been manually set. There are also PIC-assisted DDS designs, but these are more complex thatn I want, use more power then I'd like, and are not as clean as a simple voltage controlled oscillator. A number of the MicroChip MPs have 16-bit internal counters that claim to run as high as 50 MHz. The carry out of that counter could be used to cause an interrupt to extend the number of bits in the count. But you would need to precede the count chain with a gate of known and accurate count-window duration. I've thought about the subject and would try a 74AC-series flip-flop as the "gate". The gating control signal would be applied to its DC-reset. A 74HC4060 running with a "32" kHz clock crystal could provide the gating signal. Properly biasing the flip-flop's clock input might result in fairly good sensitivity. These MicroChip MPs have a pulse-width-modulated [PWM] output, but it's only 8- or 10-bit resolution. It could be dithered for more resolution, but that would require an even greater time-constant in the AFC applied to the VCO - probably intolerable. A simple, inaccurate, 8-bit D-to-A chip might be used for rough AFC voltage, with interpolation using the PWM. WARNING: All the above is just hand-waving. 73 de bob w3otc |
"W3JDR" wrote in message ... Anyone know of a PIC-based frequency locked loop for VFO control? I'm looking for something that can be programmed with a frequency word, and then it aquires and maintains the frequency. I've seen frequency 'stabilizers' but most of them just hold the frequency once it's been manually set. There are also PIC-assisted DDS designs, but these are more complex thatn I want, use more power then I'd like, and are not as clean as a simple voltage controlled oscillator. It seems to me that the PIC should be able to measure the frequency, determine the error, and operate a very simple charge-pump/VCO to put the frequency where it wants. I've seen a couple of MCU-controlled "Huff and Puff" stabilisers on the web. You'll find a couple he http://www.hanssummers.com/radio/huffpuff/contents.htm Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_heller |
"W3JDR" wrote in message ... Anyone know of a PIC-based frequency locked loop for VFO control? I'm looking for something that can be programmed with a frequency word, and then it aquires and maintains the frequency. I've seen frequency 'stabilizers' but most of them just hold the frequency once it's been manually set. There are also PIC-assisted DDS designs, but these are more complex thatn I want, use more power then I'd like, and are not as clean as a simple voltage controlled oscillator. It seems to me that the PIC should be able to measure the frequency, determine the error, and operate a very simple charge-pump/VCO to put the frequency where it wants. I've seen a couple of MCU-controlled "Huff and Puff" stabilisers on the web. You'll find a couple he http://www.hanssummers.com/radio/huffpuff/contents.htm Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_heller |
As I said in my original post, there are plenty of 'stabilizers' available
for the taking. I have also seen a few PIC frequency counter implementations that don't need any external gating. There are also plenty of PLL chips which would do the job. However, I have not seen a software application for the PIC that does it all without (hardly any) external hardware...this should be possible. What I want to do is create a tiny, low-power, stable & accurate HF frequency source module. I think I can implement it with 2 packages...the PIC and a VCO made out of biased-up CMOS inverters. I want to be able to 'hard-code' a frequency in some cases (fixed-frequency oscillator), or send an arbitrary frequency word for variable frequency control in other cases (VFO). This would be a very useful 'building-block' for making HF communications gear. The important factors for my applications are good tuning resolution, reasonable lock-up time, and minimal phase noise. Of course, defining 'how good is good enough' is somewhat subjective. Whether it's done as a PLL or an FLL is somewhat semantic as most PLL synthesizer's really don't control the short-term phase real well anyway. Joe W3JDR "W3JDR" wrote in message ... Anyone know of a PIC-based frequency locked loop for VFO control? I'm looking for something that can be programmed with a frequency word, and then it aquires and maintains the frequency. I've seen frequency 'stabilizers' but most of them just hold the frequency once it's been manually set. There are also PIC-assisted DDS designs, but these are more complex thatn I want, use more power then I'd like, and are not as clean as a simple voltage controlled oscillator. It seems to me that the PIC should be able to measure the frequency, determine the error, and operate a very simple charge-pump/VCO to put the frequency where it wants. Joe W3JDR |
As I said in my original post, there are plenty of 'stabilizers' available
for the taking. I have also seen a few PIC frequency counter implementations that don't need any external gating. There are also plenty of PLL chips which would do the job. However, I have not seen a software application for the PIC that does it all without (hardly any) external hardware...this should be possible. What I want to do is create a tiny, low-power, stable & accurate HF frequency source module. I think I can implement it with 2 packages...the PIC and a VCO made out of biased-up CMOS inverters. I want to be able to 'hard-code' a frequency in some cases (fixed-frequency oscillator), or send an arbitrary frequency word for variable frequency control in other cases (VFO). This would be a very useful 'building-block' for making HF communications gear. The important factors for my applications are good tuning resolution, reasonable lock-up time, and minimal phase noise. Of course, defining 'how good is good enough' is somewhat subjective. Whether it's done as a PLL or an FLL is somewhat semantic as most PLL synthesizer's really don't control the short-term phase real well anyway. Joe W3JDR "W3JDR" wrote in message ... Anyone know of a PIC-based frequency locked loop for VFO control? I'm looking for something that can be programmed with a frequency word, and then it aquires and maintains the frequency. I've seen frequency 'stabilizers' but most of them just hold the frequency once it's been manually set. There are also PIC-assisted DDS designs, but these are more complex thatn I want, use more power then I'd like, and are not as clean as a simple voltage controlled oscillator. It seems to me that the PIC should be able to measure the frequency, determine the error, and operate a very simple charge-pump/VCO to put the frequency where it wants. Joe W3JDR |
On Tue, 22 Jul 2003 11:44:07 +0000, W3JDR wrote:
Anyone know of a PIC-based frequency locked loop for VFO control? I'm looking for something that can be programmed with a frequency word, and then it aquires and maintains the frequency. I've seen frequency 'stabilizers' but most of them just hold the frequency once it's been manually set. There are also PIC-assisted DDS designs, but these are more complex thatn I want, use more power then I'd like, and are not as clean as a simple voltage controlled oscillator. Mine is at http://homepage.eircom.net/~ei9gq/stab.html Have a look at Hans Summers and Richard Hoskings web-pages. It seems to me that the PIC should be able to measure the frequency, determine the error, and operate a very simple charge-pump/VCO to put the frequency where it wants. Joe W3JDR What you are describing is a conventional PLL. PIC based stabilisers or 'frequency locked loops' usually have very long gate times for counting the frequency and a fairly narrow frequency control range. My circuit uses a 100mS gate time and a control range of +/- a couple of KHz. If you want to cover a larger frequency range with your VCO, you will need to use a much shorter gate time to keep tight control of the VCO frequency. This will increase the tuning steps and will also increase the phase noise on the VCO output. You soon run into the the same trade offs and compromises that you get with any PLL design. A PLL/DDS combination seems to be the best way to go. I recently built a 21MHz VFO for a 10M transceiver. The 21MHz VCO is mixed with the output from a 17MHz crystal oscillator. The resulting 4MHz signal is phase locked with a 4MHz signal from an AD9835 DDS chip. The DDS is controlled by a PIC16F84. I use the 10M rig to drive a homebrew transverter for 144MHz. I am delighted with the results. The RX is free from the usual birdies you get with a DDS VFO. The phase noise is low enough that I can operate within a few KHz of some very strong local stations on 2M SSB. 73, Ed. EI9GQ. -- Remove 'X' to reply by e-mail http://homepage.eircom.net/~ei9gq Linux 2.4.21 |
On Tue, 22 Jul 2003 11:44:07 +0000, W3JDR wrote:
Anyone know of a PIC-based frequency locked loop for VFO control? I'm looking for something that can be programmed with a frequency word, and then it aquires and maintains the frequency. I've seen frequency 'stabilizers' but most of them just hold the frequency once it's been manually set. There are also PIC-assisted DDS designs, but these are more complex thatn I want, use more power then I'd like, and are not as clean as a simple voltage controlled oscillator. Mine is at http://homepage.eircom.net/~ei9gq/stab.html Have a look at Hans Summers and Richard Hoskings web-pages. It seems to me that the PIC should be able to measure the frequency, determine the error, and operate a very simple charge-pump/VCO to put the frequency where it wants. Joe W3JDR What you are describing is a conventional PLL. PIC based stabilisers or 'frequency locked loops' usually have very long gate times for counting the frequency and a fairly narrow frequency control range. My circuit uses a 100mS gate time and a control range of +/- a couple of KHz. If you want to cover a larger frequency range with your VCO, you will need to use a much shorter gate time to keep tight control of the VCO frequency. This will increase the tuning steps and will also increase the phase noise on the VCO output. You soon run into the the same trade offs and compromises that you get with any PLL design. A PLL/DDS combination seems to be the best way to go. I recently built a 21MHz VFO for a 10M transceiver. The 21MHz VCO is mixed with the output from a 17MHz crystal oscillator. The resulting 4MHz signal is phase locked with a 4MHz signal from an AD9835 DDS chip. The DDS is controlled by a PIC16F84. I use the 10M rig to drive a homebrew transverter for 144MHz. I am delighted with the results. The RX is free from the usual birdies you get with a DDS VFO. The phase noise is low enough that I can operate within a few KHz of some very strong local stations on 2M SSB. 73, Ed. EI9GQ. -- Remove 'X' to reply by e-mail http://homepage.eircom.net/~ei9gq Linux 2.4.21 |
In article , "W3JDR"
writes: The important factors for my applications are good tuning resolution, reasonable lock-up time, and minimal phase noise. Of course, defining 'how good is good enough' is somewhat subjective. Whether it's done as a PLL or an FLL is somewhat semantic as most PLL synthesizer's really don't control the short-term phase real well anyway. Short-term phase stability almost always lies in the VCO design with some disturbance possible by an incorrect loop filter. That has little to do whether the VCO is used with a PLL or DDS. To be phase-stable (i.e., reduce short-term jitter), the VCO supply rails should be bypassed adequately well up into the RF range of the VCO and the control voltage line absolutely free from any loop-induced pickup almost to the VCO's RF range. Iron powder or ferrite beads, even slabs of the stuff, can halp on the control line. Stability also involves using whatever active device in the oscillator at its optimum lowest-noise point...that's device dependent and not all manufacturers supply such data. In truth, I've never had experience with the PLL or DDS dividers as an integral part of the frequency control determining processor. I've always had to work some to make the external-divider kind lay down and be nice. I would imagine there's more fun and games with a combined type using a Microchip processor being both controller and divider. :-) Len Anderson retired (from regular hours) electronic engineer person |
In article , "W3JDR"
writes: The important factors for my applications are good tuning resolution, reasonable lock-up time, and minimal phase noise. Of course, defining 'how good is good enough' is somewhat subjective. Whether it's done as a PLL or an FLL is somewhat semantic as most PLL synthesizer's really don't control the short-term phase real well anyway. Short-term phase stability almost always lies in the VCO design with some disturbance possible by an incorrect loop filter. That has little to do whether the VCO is used with a PLL or DDS. To be phase-stable (i.e., reduce short-term jitter), the VCO supply rails should be bypassed adequately well up into the RF range of the VCO and the control voltage line absolutely free from any loop-induced pickup almost to the VCO's RF range. Iron powder or ferrite beads, even slabs of the stuff, can halp on the control line. Stability also involves using whatever active device in the oscillator at its optimum lowest-noise point...that's device dependent and not all manufacturers supply such data. In truth, I've never had experience with the PLL or DDS dividers as an integral part of the frequency control determining processor. I've always had to work some to make the external-divider kind lay down and be nice. I would imagine there's more fun and games with a combined type using a Microchip processor being both controller and divider. :-) Len Anderson retired (from regular hours) electronic engineer person |
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