In article yfGwc.23554$DV4.9103@clgrps13, says...

Behold, Leon Heller signalled from keyed 4-1000A filament:

"Gregg" wrote in message
news:COwwc.24725$jl6.6833@edtnps89...
I'm building a SWRX with PLL frequency generator and need a 1/2 dozen
of these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

I'd use a CPLD - it'll be faster, cheaper and take up less board space.
You can use it for the rest of the logic as well, including the phase
detector.

73, Leon

Hi Leon,

Thanks. But as a tubehead myself, how on earth do I go about doing this?

CPLDs are one option, though I don't know enough about them as yet
to say for certain how easy or difficult it would be to design one in.

Here are a couple of links that may help.

http://www.xilinx.com/xlnx/xil_prodc...ldle arn_page

http://www.xilinx.com/xlnx/xil_prodc...tle=design_kit

The designer's kit will run you about $50.

Happy hunting.


--
Dr. Anton T. Squeegee, Director, Dutch Surrealist Plumbing Institute.
(Known to some as Bruce Lane, ARS KC7GR,
kyrrin (a/t) bluefeathertech[d=o=t]calm -- www.bluefeathertech.com
"If Salvador Dali had owned a computer, would it have been equipped
with surreal ports?"

Dr. Anton T. Squeegee ) writes:
In article COwwc.24725$jl6.6833@edtnps89, says...

I'm building a SWRX with PLL frequency generator and need a 1/2 dozen of
these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

The 74HC390, a dual decade counter in one package, has a maximum
clock frequency of 66MHz, and is readily available (or at least a lot
more so than the AS or S package -- less power draw too).

But given that the '192 is programmable, and this is a synthesizer
application, I suspect he wants the '192 for the divide by N counter
chain, not a fixed divider.

Michael VE2BVW

Dr. Anton T. Squeegee ) writes:
In article COwwc.24725$jl6.6833@edtnps89, says...

I'm building a SWRX with PLL frequency generator and need a 1/2 dozen of
these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

The 74HC390, a dual decade counter in one package, has a maximum
clock frequency of 66MHz, and is readily available (or at least a lot
more so than the AS or S package -- less power draw too).

But given that the '192 is programmable, and this is a synthesizer
application, I suspect he wants the '192 for the divide by N counter
chain, not a fixed divider.

Michael VE2BVW

"Gregg" wrote in message
news:COwwc.24725$jl6.6833@edtnps89...
I'm building a SWRX with PLL frequency generator and need a 1/2 dozen of
these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

Have you considered the 74AC series? The 74ac74 will go well above 100 MHz.
Prescale by 4 with these and then use slower presettable counters.

Or the 74HC/HCT4059 is guaranteed to do over 20 MHz and typically 50 MHz and
is a 16-bit presetable counter. Probably very hard to find these days.

"Gregg" wrote in message
news:COwwc.24725$jl6.6833@edtnps89...
I'm building a SWRX with PLL frequency generator and need a 1/2 dozen of
these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

Have you considered the 74AC series? The 74ac74 will go well above 100 MHz.
Prescale by 4 with these and then use slower presettable counters.

Or the 74HC/HCT4059 is guaranteed to do over 20 MHz and typically 50 MHz and
is a 16-bit presetable counter. Probably very hard to find these days.

You can check out Xilinx's free design SW (includes CPLD stuff)
starting he

http://www.xilinx.com/xlnx/xebiz/des...DS-ISE-WEBPACK

I guess Altera and Atmel also have free or low-cost design solutions.
See, for example, the Atmel ATF15xx-DK2 sold by DigiKey and others.
But the problem is that you still have to actually program the parts,
and that can be a barrier. It's just something you have to commit to
doing, and perhaps spending either some time or some money to put the
right environment in place to make the programming easy. For example,
you can buy a JTAG programmer from Xilinx that plugs into the parallel
port of a PC, and perhaps they still provide an ap note with the
schematic if you wanted to make your own. However, once you do get
over the barrier, the rewards can be great: you can pack quite a lot
into a single CPLD, and you can change it just by re-programming when
you discover a mistake or an improvement. The re-programming can be
(is generally best done) in-circuit, so there's no unsoldering
involved. A single tiny CPLD can have hundreds of flip-flops, with
associated logic.

On the other hand, have you investigated other solutions? I didn't
see your original posting, but suppose that there must be 74AC/74ACT
parts that will clock plenty fast enough, and there are some nice PLL
chips from folks like Analog Devices and National Semiconductor with
built-in programmable dividers for both reference and oscillator
inputs, and they can go up into the GHz region for the oscillator
inputs. (They may appear at first to have TOO HIGH a minimum
frequency, but if you get a dual one designed for both RF and IF
range, you'll probably find that the IF range section will go low
enough.) They are compact and inexpensive.

Cheers,
Tom


Gregg wrote in message news:yfGwc.23554$DV4.9103@clgrps13...
Behold, Leon Heller signalled from keyed 4-1000A filament:

"Gregg" wrote in message
news:COwwc.24725$jl6.6833@edtnps89...
I'm building a SWRX with PLL frequency generator and need a 1/2 dozen
of these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

I'd use a CPLD - it'll be faster, cheaper and take up less board space.
You can use it for the rest of the logic as well, including the phase
detector.

73, Leon

Hi Leon,

Thanks. But as a tubehead myself, how on earth do I go about doing this?

You can check out Xilinx's free design SW (includes CPLD stuff)
starting he

http://www.xilinx.com/xlnx/xebiz/des...DS-ISE-WEBPACK

I guess Altera and Atmel also have free or low-cost design solutions.
See, for example, the Atmel ATF15xx-DK2 sold by DigiKey and others.
But the problem is that you still have to actually program the parts,
and that can be a barrier. It's just something you have to commit to
doing, and perhaps spending either some time or some money to put the
right environment in place to make the programming easy. For example,
you can buy a JTAG programmer from Xilinx that plugs into the parallel
port of a PC, and perhaps they still provide an ap note with the
schematic if you wanted to make your own. However, once you do get
over the barrier, the rewards can be great: you can pack quite a lot
into a single CPLD, and you can change it just by re-programming when
you discover a mistake or an improvement. The re-programming can be
(is generally best done) in-circuit, so there's no unsoldering
involved. A single tiny CPLD can have hundreds of flip-flops, with
associated logic.

On the other hand, have you investigated other solutions? I didn't
see your original posting, but suppose that there must be 74AC/74ACT
parts that will clock plenty fast enough, and there are some nice PLL
chips from folks like Analog Devices and National Semiconductor with
built-in programmable dividers for both reference and oscillator
inputs, and they can go up into the GHz region for the oscillator
inputs. (They may appear at first to have TOO HIGH a minimum
frequency, but if you get a dual one designed for both RF and IF
range, you'll probably find that the IF range section will go low
enough.) They are compact and inexpensive.

Cheers,
Tom


Gregg wrote in message news:yfGwc.23554$DV4.9103@clgrps13...
Behold, Leon Heller signalled from keyed 4-1000A filament:

"Gregg" wrote in message
news:COwwc.24725$jl6.6833@edtnps89...
I'm building a SWRX with PLL frequency generator and need a 1/2 dozen
of these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

I'd use a CPLD - it'll be faster, cheaper and take up less board space.
You can use it for the rest of the logic as well, including the phase
detector.

73, Leon

Hi Leon,

Thanks. But as a tubehead myself, how on earth do I go about doing this?

You can check out Xilinx's free design SW (includes CPLD stuff)
starting he

http://www.xilinx.com/xlnx/xebiz/des...DS-ISE-WEBPACK

I guess Altera and Atmel also have free or low-cost design solutions.
See, for example, the Atmel ATF15xx-DK2 sold by DigiKey and others.
But the problem is that you still have to actually program the parts,
and that can be a barrier. It's just something you have to commit to
doing, and perhaps spending either some time or some money to put the
right environment in place to make the programming easy. For example,
you can buy a JTAG programmer from Xilinx that plugs into the parallel
port of a PC, and perhaps they still provide an ap note with the
schematic if you wanted to make your own. However, once you do get
over the barrier, the rewards can be great: you can pack quite a lot
into a single CPLD, and you can change it just by re-programming when
you discover a mistake or an improvement. The re-programming can be
(is generally best done) in-circuit, so there's no unsoldering
involved. A single tiny CPLD can have hundreds of flip-flops, with
associated logic.

On the other hand, have you investigated other solutions? I didn't
see your original posting, but suppose that there must be 74AC/74ACT
parts that will clock plenty fast enough, and there are some nice PLL
chips from folks like Analog Devices and National Semiconductor with
built-in programmable dividers for both reference and oscillator
inputs, and they can go up into the GHz region for the oscillator
inputs. (They may appear at first to have TOO HIGH a minimum
frequency, but if you get a dual one designed for both RF and IF
range, you'll probably find that the IF range section will go low
enough.) They are compact and inexpensive.

Cheers,
Tom


Gregg wrote in message news:yfGwc.23554$DV4.9103@clgrps13...
Behold, Leon Heller signalled from keyed 4-1000A filament:

"Gregg" wrote in message
news:COwwc.24725$jl6.6833@edtnps89...
I'm building a SWRX with PLL frequency generator and need a 1/2 dozen
of these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

I'd use a CPLD - it'll be faster, cheaper and take up less board space.
You can use it for the rest of the logic as well, including the phase
detector.

73, Leon

Hi Leon,

Thanks. But as a tubehead myself, how on earth do I go about doing this?

You can check out Xilinx's free design SW (includes CPLD stuff)
starting he

http://www.xilinx.com/xlnx/xebiz/des...DS-ISE-WEBPACK

I guess Altera and Atmel also have free or low-cost design solutions.
See, for example, the Atmel ATF15xx-DK2 sold by DigiKey and others.
But the problem is that you still have to actually program the parts,
and that can be a barrier. It's just something you have to commit to
doing, and perhaps spending either some time or some money to put the
right environment in place to make the programming easy. For example,
you can buy a JTAG programmer from Xilinx that plugs into the parallel
port of a PC, and perhaps they still provide an ap note with the
schematic if you wanted to make your own. However, once you do get
over the barrier, the rewards can be great: you can pack quite a lot
into a single CPLD, and you can change it just by re-programming when
you discover a mistake or an improvement. The re-programming can be
(is generally best done) in-circuit, so there's no unsoldering
involved. A single tiny CPLD can have hundreds of flip-flops, with
associated logic.

On the other hand, have you investigated other solutions? I didn't
see your original posting, but suppose that there must be 74AC/74ACT
parts that will clock plenty fast enough, and there are some nice PLL
chips from folks like Analog Devices and National Semiconductor with
built-in programmable dividers for both reference and oscillator
inputs, and they can go up into the GHz region for the oscillator
inputs. (They may appear at first to have TOO HIGH a minimum
frequency, but if you get a dual one designed for both RF and IF
range, you'll probably find that the IF range section will go low
enough.) They are compact and inexpensive.

Cheers,
Tom


Gregg wrote in message news:yfGwc.23554$DV4.9103@clgrps13...
Behold, Leon Heller signalled from keyed 4-1000A filament:

"Gregg" wrote in message
news:COwwc.24725$jl6.6833@edtnps89...
I'm building a SWRX with PLL frequency generator and need a 1/2 dozen
of these chips. They are unobtanium from my Vancouver suppliers.

I need the speed of AS or S because the master osc. will be 60-90 MHz.

I'd use a CPLD - it'll be faster, cheaper and take up less board space.
You can use it for the rest of the logic as well, including the phase
detector.

73, Leon

Hi Leon,

Thanks. But as a tubehead myself, how on earth do I go about doing this?

Behold, Leon Heller signalled from keyed 4-1000A filament:

"Gregg" wrote in message
news:yfGwc.23554$DV4.9103@clgrps13...
Behold, Leon Heller signalled from keyed 4-1000A filament:

"Gregg" wrote in message
news:COwwc.24725$jl6.6833@edtnps89...
I'm building a SWRX with PLL frequency generator and need a 1/2
dozen of these chips. They are unobtanium from my Vancouver
suppliers.

I need the speed of AS or S because the master osc. will be 60-90
MHz.

I'd use a CPLD - it'll be faster, cheaper and take up less board
space. You can use it for the rest of the logic as well, including
the phase detector.

73, Leon

Hi Leon,

Thanks. But as a tubehead myself, how on earth do I go about doing
this?

You've got a lot of learning to do. 8-)

Try this web page of mine:

http://www.geocities.com/leon_heller/pld_starter.html

Leon

Thanks Leon! :-)

I'm a fast learner, you rock!

--
Gregg
*It's probably useful, even if it can't be SPICE'd*
http://geek.scorpiorising.ca