George Smart - M1GEO

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Experiments with Phase-Frequency Detectors

Posted: 12 Feb 2020 10:12 AM PST
https://www.george-smart.co.uk/2020/...ncy-detectors/



Over the past few evenings, I have been experimenting with phase-frequency
detectors. I have an upcoming project that requires the use of one, and, I
figured Id refresh my memory on them. I ended up using my Lattice MachXO2
breakout board as the development platform.




The first step was to divide a 10 MHz crystal oscillator down to 10 kHz.
That was easily done with a counter, counting from 0 to 499, and then
resetting to 0. Every reset would simultaneously toggle an output bit, with
the net result being a square-wave clock on the output bit, periodic every
1000 cycles of the input. A divide by 1000 counter.




Next was to understand the Phase-Frequency Detector (PFD). This is commonly
referred to as a Type 2 detector, since it detects not only phase
difference but frequency difference. This means that the PLL will only ever
lock to the fundamental frequency, and not harmonics. It also means that
when the loop is unlocked, the PFD knows which way to drive the VCO to
regain lock. A Type 1 detector only uses phase information, and so drives
the oscillator in the direction of the phase difference until the loop
locks as a result, Type 2 detectors lock quicker.




The Type 2 detector has two outputs, up and down, which pulse for the
required direction with a duty cycle proportional to the phase difference.




I spent a few days designing and simulating the PFD using the Aldec
Active-HDL simulator to confirm that my circuit did indeed perform as
expected:








I then added a simple lock detector, which set a locked signal high if the
phases were in lock for the past 10 cycles as a proof of concept. In
reality, a much longer observation window will be used. It is possible to
see the lock signal becomes high after 10 cycles.








The final stage of this project snippet was to test on real hardware. The
Verilog code was pushed through synthesis, place and route, and a
configuration file for the Lattice FPGA generated. This was then programmed
into the board, and the board taken to the lab you can see all the main
parts of the setup in the photo below.








Below, you can see the scope traces from the probes in the lab bench
photo. The yellow trace shows the 10 MHz VCO frequency from the Trimble
34310-T2 OCXO. The green trace is a debug from the FPGA output showing the
10 MHz signal divided down 10 kHz. The blue trace is GPS locked 10 kHz
reference output. Finally, the purple is phase detector output, here from
the down output of the detector since we see that the divided VCO output
(green) slightly leads the GPS reference (blue). The up output is at
logic-0 throughout.








The next part of the project is to create the charge pump circuit which
converts the up and down signals into an analogue control voltage for the
VCO. I had better get ordering some parts